A manufacturable shallow trench isolation process for sub-0.2 um DRAM technologies

Author

Lien, W.Y. ; Yeh, W.G. ; Li, C.H. ; Tu, K.C. ; Chang, I.H. ; Chu, H.C. ; Liaw, W.R. ; Lee, H.F. ; Chou, H.M. ; Chen, C.Y. ; Chi, M.H.

Author_Institution

R&D, Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan

fYear

2002

fDate

6/24/1905 12:00:00 AM

Firstpage

11

Lastpage

16

Abstract

A highly manufacturable and defect-free shallow trench isolation (STI) process is demonstrated by using 64M DRAM as a sensitive monitor. In the STI flow, a special sequence of extra anneal (1100C) after corner oxidation (i.e., liner oxide) and an RTA (1000C) anneal after HDP CVD oxide deposition can result in a significantly higher yield in 64M DRAM by effectively reducing silicon stress related substrate defects.

Keywords

DRAM chips; annealing; integrated circuit yield; isolation technology; oxidation; plasma CVD coatings; rapid thermal annealing; 0.2 micron; 1000 C; 1100 C; 64 Mbit; DRAM technology; HDP CVD oxide deposition; RTA; Si; annealing; corner oxidation; liner oxide; semiconductor manufacturing; shallow trench isolation; silicon stress; substrate defect; yield; Annealing; Etching; Isolation technology; Manufacturing processes; Oxidation; Random access memory; Semiconductor device manufacture; Silicon compounds; Substrates; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing 2002 IEEE/SEMI Conference and Workshop

Print_ISBN

0-7803-7158-5

Type

conf

DOI

10.1109/ASMC.2002.1001565

Filename

1001565