DocumentCode
1578904
Title
An Efficient Architecture for Entropy-Based Best-Basis Algorithm
Author
Aroutchelvame, S.M. ; Raahemifar, Kaamran
Author_Institution
Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, Ont., Canada
fYear
2006
Firstpage
3281
Lastpage
3284
Abstract
In this work, we propose an architecture for the wavelet-packet based best-basis algorithm for images using Shannon entropy as cost function. The algorithm for the logarithm implementation for integers using Taylor series is also proposed to implement Shannon entropy. The proposed architecture includes the architectures for the best-tree selection. The execution time of the proposed hardware for the best-basis algorithm for images is compared to its software implementation. The proposed best-basis architecture has been described in VHDL at the RTL level, simulated successfully for its functional correctness and implemented in an FPGA.
Keywords
entropy; field programmable gate arrays; hardware description languages; image processing; series (mathematics); wavelet transforms; FPGA; RTL level; Shannon entropy; Taylor series; VHDL; best-basis algorithm; best-tree selection; cost function; hardware execution time; image analysis; logarithm implementation; wavelet-packet architecture; Arithmetic; Clocks; Computer architecture; Cost function; Entropy; Field programmable gate arrays; Hardware; Table lookup; Taylor series; Wavelet packets; Best-basis architecture; Shannon;
fLanguage
English
Publisher
ieee
Conference_Titel
Image Processing, 2006 IEEE International Conference on
Conference_Location
Atlanta, GA
ISSN
1522-4880
Print_ISBN
1-4244-0480-0
Type
conf
DOI
10.1109/ICIP.2006.312786
Filename
4107271
Link To Document