An Enhanced Path Delay Fault Simulator for Combinational Circuits

This paper presents an enhanced path delay fault simulator for combinational circuits. The main objective of this work is to improve the simulation time of path delay fault testing. Our experiments consider K-longest path sets of ISCAS´85 benchmark circuits, and 10M single input change (SIC) test patterns were applied and repeated ten times in order to cover statistical variations. The experimental results show that the modified path selection and simulation algorithm provides good fault coverage and 20% improved simulation time as an average speed-up factor.