Title :
An Enhanced Path Delay Fault Simulator for Combinational Circuits
Author :
Manikandan, P. ; Larsen, Bjørn B. ; Aas, Einar J.
Author_Institution :
Dept. of Electron. & Telecommun., Norwegian Univ. of Sci. & Technol., Trondheim, Norway
Abstract :
This paper presents an enhanced path delay fault simulator for combinational circuits. The main objective of this work is to improve the simulation time of path delay fault testing. Our experiments consider K-longest path sets of ISCAS´85 benchmark circuits, and 10M single input change (SIC) test patterns were applied and repeated ten times in order to cover statistical variations. The experimental results show that the modified path selection and simulation algorithm provides good fault coverage and 20% improved simulation time as an average speed-up factor.
Keywords :
combinational circuits; delays; fault diagnosis; logic testing; statistical analysis; ISCAS´85 benchmark circuits; combinational circuits; enhanced path delay fault simulator; path delay fault testing; single input change test patterns; statistical variations; Circuit faults; Delay; Integrated circuit modeling; Logic gates; Silicon carbide; Software; Testing; Combinational circuits; Path delay fault test; Single-input change; Test Stimuli;
Conference_Titel :
Digital System Design (DSD), 2011 14th Euromicro Conference on
Conference_Location :
Oulu
Print_ISBN :
978-1-4577-1048-3
DOI :
10.1109/DSD.2011.52
