Analyzing Area Penalty of 32-Bit Fault Tolerant ALU Using BCH Code

Author

Khorasani, Vahid ; Vahdat, Bijan Vosoughi ; Mortazavi, Mohammad

Author_Institution

Dept. of Electr. Eng., Sharif Univ. of Technol., Tehran, Iran

fYear

2011

Firstpage

409

Lastpage

413

Abstract

In this paper we have presented a hardware implementation of 32-bit Fault-tolerant ALU (Arithmetic and Logic Unit) which is compared with the current techniques, Residue code, Triple Modular Redundancy (TMR) with single voting and TMR with triplicated voter that are widely used in space application to mitigate the upsets, in terms of area penalty. We consider BCH (Bose, Chaudhuri, and Hocquenghem) codec (encoder, decoder) using the prototyping FPGA (Field Programmable Gate Array). The new implementation of ALU employing BCH code on Spartan-3 FPGA has been provided. The results show that our fault tolerant method has the lowest hardware overhead and it can correct any 5-bit error in any position of 32-bit input registers of ALU.

Keywords

BCH codes; fault tolerance; field programmable gate arrays; logic circuits; logic testing; BCH code; Bose-Chaudhuri-and-Hocquenghem codec; TMR; area penalty; arithmetic-and-logic unit; decoder; encoder; fault tolerant ALU; field programmable gate array; prototyping FPGA; residue code; triple modular redundancy; word length 32 bit; Decoding; Fault tolerant systems; Hardware; Polynomials; Redundancy; Registers; ALU; BCH codes; Decoding; Encoding; FPGA; Fault tolerant; Residue codes; TMR;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital System Design (DSD), 2011 14th Euromicro Conference on

Conference_Location

Oulu

Print_ISBN

978-1-4577-1048-3

Type

conf

DOI

10.1109/DSD.2011.113

Filename

6037439