DocumentCode
1579145
Title
Architectures for Fast Modular Multiplication
Author
Aris, Ahmet ; Ors, Berna ; Saldamli, Gokay
Author_Institution
Fac. of Electr. & Electron. Eng., Istanbul Tech. Univ., Istanbul, Turkey
fYear
2011
Firstpage
434
Lastpage
437
Abstract
Modular multiplication is the key ingredient needed to realize most public-key cryptographic primitives. In a modular setting, multiplications are carried in two steps: namely a usual integer arithmetic followed by a reduction step. Progress in any of these steps naturally improves the modular multiplication but it is not possible to interleave the best algorithms of these stages. In this study, we propose architectures for recently proposed method of interleaving the Karatsuba-Ofman multiplier and bipartite modular reduction on the upper most layer of Karatsuba-Ofman´s recursion. We manage to come up with a high performance modular multiplication architecture by taking the advantage of a fast multiplication and a parallel reduction method.
Keywords
public key cryptography; Karatsuba-Ofman multiplier; Karatsuba-Ofman recursion; bipartite modular reduction; fast modular multiplication; integer arithmetic; modular multiplication architecture; parallel reduction method; public key cryptographic primitives; reduction step; Clocks; Computer architecture; Elliptic curve cryptography; Hardware; Registers; Signal processing algorithms; Bipartite modular multiplication; Karatsuba-Ofman Algorithm; interleaved multiplication; modular arithmetic;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital System Design (DSD), 2011 14th Euromicro Conference on
Conference_Location
Oulu
Print_ISBN
978-1-4577-1048-3
Type
conf
DOI
10.1109/DSD.2011.60
Filename
6037444
Link To Document