DocumentCode
1579300
Title
ASIC manufacturability simulation
Author
Eiseman, Jon ; Chadha, Rakesh ; Chang, Foong-Charn ; Chen, Chin-Fu
fYear
1993
Firstpage
310
Lastpage
319
Abstract
In this tutorial, the use of simulation techniques to improve the manufacturability yield of ASIC devices is described. ASIC manufacturability simulation procedures are illustrated with the help of various practical examples. Use of ASIC manufacturability simulation as part of standard design methodology at AT&T has been shown to improve the yield of ASIC devices, and it also helps reduce the ASIC design interval
Keywords
Application specific integrated circuits; Clocks; Delay; Design methodology; Discrete event simulation; Logic design; Logic devices; Manufacturing processes; Testing; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-1375-5
Type
conf
DOI
10.1109/ASIC.1993.410729
Filename
410729
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