Configurable two-dimensional linear feedback shifter registers for built-in self-test

A configurable 2D LFSR based test generator and an automated synthesis procedure is presented. Without storage of test patterns, a 2D LFSR based test pattern generator can generate a sequence of pre-computed test patterns (detecting random-pattern-resistant faults) and followed by random patterns (detecting random-pattern-detectable). The hardware overhead is decreased considerably through configuration. The configurable 2D LFSR test generator can be adopted in two basic BIST execution options: test-per-clock (parallel BIST) and test-per-scan (serial BIST). Experimental results of test-per-clock and test-per-scan BIST of benchmark circuits demonstrate the effectiveness of the proposed technique. The configurable 2D LFSR can also be adopted in chip-level and system-on-chip (SoC) BIST.