DocumentCode :
1579594
Title :
SoC and Board Modeling for Processor-Centric Board Testing
Author :
Tsertov, Anton ; Ubar, Raimund ; Jutman, Artur ; Devadze, Sergei
Author_Institution :
Dept. of Comput. Eng., Tallinn Univ. of Technol., Tallinn, Estonia
fYear :
2011
Firstpage :
575
Lastpage :
582
Abstract :
Many contemporary electronic systems are based on System-on-Chips (SoC) such as micro-controllers or signal processors that communicate with many peripheral devices on the system board and beyond. While, SoC test was a topic of extremely high interest during the last decade, the test beyond SoCs didn\´t get much attention after introduction of Boundary Scan (BS) 30 years ago. It is not a surprise that the restricted capabilities of BS with respect of such modern challenges as dynamic (timing-accurate), at-speed and high-speed testing as well as in-system programming create considerable troubles for test engineers in production environments. In this paper, we point out particular challenges in testing the system\´s infrastructure beyond the SoCs as well as propose a general modeling methodology for test automation for microprocessor SoC-based system boards. The new so-called "Lego-style" test automation methodology forms a complimentary solution to traditional boundary scan. Together, they provide extended fault coverage that targets shorts, opens, stuck-at faults as well as dynamic faults (e.g. delays and transition faults). The "Legostyle" model allows reducing the labour effort drastically once the library of model components is created.
Keywords :
integrated circuit modelling; integrated circuit testing; microcontrollers; system-on-chip; Lego-style test automation methodology; SoC test; board modeling; boundary scan; contemporary electronic systems; dynamic faults; fault coverage; in-system programming; microcontrollers; microprocessor SoC-based system boards; peripheral devices; processor-centric board testing; system-on-chips; Automation; Data models; Libraries; Program processors; Random access memory; System-on-a-chip; Testing; JTAG; decision diagrams; emulation-based test; modeling; test synthesis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design (DSD), 2011 14th Euromicro Conference on
Conference_Location :
Oulu
Print_ISBN :
978-1-4577-1048-3
Type :
conf
DOI :
10.1109/DSD.2011.79
Filename :
6037463
Link To Document :
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