DocumentCode :
1579919
Title :
An ARM7 processor with the Modified Multiplier and the Flip-Flop Based Pipelines
Author :
Cho, Hyun Woo ; Lee, Ahn Woo ; Chi, Hua Jun ; Song, Seung Won ; Gwon, Gyeong Su ; Park, Ju Sung
Author_Institution :
Dept. of Electron. Eng., Pusan Nat. Univ., Busan
fYear :
2006
Firstpage :
68
Lastpage :
71
Abstract :
The flip-flop base ARM7 core is designed and fabricated with 0.18 mum CMOS process. The designed processor core can be easily synthesized with the various CMOS libraries because it doesn´t have the clock skew and race problem. The conventional ARM7 core has 32times8 multiplier, but we modified the multiplier with 32times16 type to improve the performance of the core. The multiplier is optimized in the point of the operating speed and the gates count. The fabricated chip is tested by the various methods, such as the single instruction test and the instruction combination test, and the application programs. According to the test results, the designed processor carries out the 462 instructions of the processor and the several application algorithms, and the operating at the 98 MHz clock rate.
Keywords :
CMOS analogue integrated circuits; flip-flops; multiplying circuits; ARM7 processor; CMOS process; flip-flop based pipelines; instruction combination test; modified multiplier; processor core; single instruction test; CMOS process; Clocks; Flip-flops; Latches; Logic; Pipelines; Process design; Reduced instruction set computing; Testing; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Strategic Technology, The 1st International Forum on
Conference_Location :
Ulsan
Print_ISBN :
1-4244-0426-6
Electronic_ISBN :
1-4244-0427-4
Type :
conf
DOI :
10.1109/IFOST.2006.312249
Filename :
4107314
Link To Document :
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