Self-calibrating differential predictive floating-point analog-to-digital converter

Various architectures for floating-point analog-to-digital converters (FP-ADC) have been conceived. The highest conversion rates were achieved, to the precision´s detriment, by employing flash analog-to-digital converters as basic building blocks. This paper proposes a new architecture that contains a high-precision, low-rate, analog-to-digital converter that periodically performs calibration cycles to compensate for the inaccuracies introduced in the measurement process by the components´ parameters drift. Besides a better accuracy, the proposed solution provides a higher reliability of FP-ADC operation.