Title :
On the Efficiency of Design Time Evaluation of the Resistance to Power Attacks
Author :
Barenghi, Alessandro ; Bertoni, Guido ; De Santis, F. ; Melzani, Filippo
Author_Institution :
Dipt. di Elettron. e Inf., Politec. di Milano, Milan, Italy
Abstract :
Side-channel attacks are a realistic threat to the security of real world implementations of cryptographic algorithms. In order to evaluate the resistance of designs against power analysis attacks, power values obtained from circuit simulations in early design phases offer two distinct advantages: First, they offer fast feedback loops to designers, second the number of redesigns can be reduced. This work investigates the accuracy of design time power estimation tools in assessing the security level of a device against differential power attacks.
Keywords :
cryptography; circuit simulations; cryptographic algorithm; design time evaluation; design time power estimation tools; differential power attacks; fast feedback loops; power analysis attacks; security; side-channel attacks; Correlation; Encryption; Integrated circuit modeling; Power measurement; Semiconductor device measurement; Voltage measurement; Side-channel attacks; design time security;
Conference_Titel :
Digital System Design (DSD), 2011 14th Euromicro Conference on
Conference_Location :
Oulu
Print_ISBN :
978-1-4577-1048-3
DOI :
10.1109/DSD.2011.103
