DocumentCode
1580248
Title
Yield learning and the sources of profitability in semiconductor manufacturing and process development
Author
Weber, Charles
Author_Institution
Sloan Sch. of Manage., MIT, Cambridge, MA, USA
fYear
2002
fDate
6/24/1905 12:00:00 AM
Firstpage
324
Lastpage
329
Abstract
A numerical model that identifies the high-leverage variables associated with profitability in semiconductor manufacturing is presented. Varying the parameters of the model demonstrates that a rapid yield-learning rate determines profitability more than any other factor does. Factors such as ramping up early, adding fab capacity, depressing the terminal fault density, and shrinking die size all yield diminishing returns. The model also suggests that preparations in the early stages of process development are the key to successful yield learning.
Keywords
integrated circuit economics; integrated circuit modelling; integrated circuit yield; semiconductor process modelling; die size shrinking; fab capacity; high-leverage variables; numerical model; process development; profitability; ramping up; semiconductor manufacturing; terminal fault density; yield-learning rate; Circuit faults; Costs; Electronics industry; Integrated circuit modeling; Manufacturing processes; Production; Profitability; Semiconductor device manufacture; Semiconductor device modeling; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing 2002 IEEE/SEMI Conference and Workshop
Print_ISBN
0-7803-7158-5
Type
conf
DOI
10.1109/ASMC.2002.1001627
Filename
1001627
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