Title :
Output voltage estimation of a floating interconnect line caused by a hard open in 90nm ICs
Author :
Manabe, Katsuya ; Yamada, Yuichi ; Yotsuyanagi, Hiroyuki ; Tsutsumi, Toshiyuki ; Yamazaki, Koji ; Higami, Yoshinobu ; Takahashi, Hiroshi ; Takamatsu, Yuzo ; Hashizume, Masaki
Author_Institution :
Kagawa Nat. Coll. of Technol., Kagawa, Japan
Abstract :
Faulty effects caused by a hard open defect at an interconnect line in a 90nm CMOS IC are analyzed by device simulation in this paper. The simulation results reveal us that output voltage of the floating interconnect line is obtained as linear sum of effects from logic signals of the adjacent interconnect lines and the defective one. Also, an estimation model of voltage at the floating interconnect line is proposed. Feasibility of the estimation is examined in this paper. The result shows us that the voltage can be estimated within error of about 0.03V.
Keywords :
CMOS logic circuits; errors; estimation theory; integrated circuit interconnections; integrated circuit modelling; CMOS logic IC; device simulation; estimate error; faulty effects; floating interconnect line; hard open defect; logic signals; output voltage estimation; size 90 nm; voltage estimation model; Circuit faults; Integrated circuit interconnections; Integrated circuit modeling; Layout; Metals; Wires;
Conference_Titel :
Communications and Information Technologies (ISCIT), 2010 International Symposium on
Conference_Location :
Tokyo
Print_ISBN :
978-1-4244-7007-5
Electronic_ISBN :
978-1-4244-7009-9
DOI :
10.1109/ISCIT.2010.5665062
