Title :
A hierarchical approach to cost analysis for next generation semiconductor processes
Author :
Sandell, Raka ; Pierce, Neal G.
Author_Institution :
Adv. Products R&D Lab., Motorola Inc., Austin, TX, USA
fDate :
6/24/1905 12:00:00 AM
Abstract :
Introduction of next generation semiconductor technologies gets progressively harder and more expensive with each node in the Semiconductor Industry Association (SIA) roadmap. True to tradition, the 0.1-micron node promises to provide a new set of processing complexities and significant capital investment as well as associated manufacturing costs. We have developed a methodology to analyze different process and equipment alternatives, in order to ultimately reduce the capital investment and overall manufacturing cost of wafers through this process. This approach is hierarchical in nature; in other words, it first aids with analysis of alternatives at a process step level and then these results are incorporated in the analysis of the total wafer and die cost at the macro process flow level. A Visual Basic based tool has been developed to enable this analysis.
Keywords :
costing; integrated circuit economics; integrated circuit modelling; integrated circuit yield; production engineering computing; semiconductor process modelling; Visual Basic based tool; capital investment; cost analysis; cost of ownership; die cost; hierarchical approach; macro process flow level; manufacturing costs; next generation semiconductor processes; process scenarios; process step level; processing complexities; total wafer cost; yield indifference curves; Costs; Investments; Laboratories; Manufacturing processes; Production facilities; Research and development; Semiconductor device manufacture; Semiconductor device modeling; Semiconductor process modeling; Virtual manufacturing;
Conference_Titel :
Advanced Semiconductor Manufacturing 2002 IEEE/SEMI Conference and Workshop
Print_ISBN :
0-7803-7158-5
DOI :
10.1109/ASMC.2002.1001628
