FPGA architectures for ASIC hardware emulators

The increasing complexity available in application-specific integrated circuits (ASICs) and the requirement for reduced design time have increased the importance of hardware emulators for ASIC system verification prior to first silicon. The authors review current ASIC hardware emulators based on field programmable gate arrays (FPGAs), including their limitations and constraints. Based on these characteristics, FPGA kernel architectures and related technologies are identified that will significantly improve the performance and capabilities of ASIC hardware emulators