A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers

As process technology is scaled down, a typical system on a chip (SoC) becomes denser. In scaled process technology, process variation becomes greater and increasingly affects the SoC circuits. Process variation strongly affects Network-on-Chips (NoCs), which have a synchronous network across the chip: its network frequency is degraded. As described herein, we propose a process-variation-adaptive NoC with a variation-adaptive variable-cycle router (VAVCR). The proposed VAVCR can configure its cycle latency adaptively, corresponding to process variation. It can increase the network frequency, which is limited by the slowest network component in a conventional router. The total execution time reduction of the proposed VAVCR is 14.9%, on average, for five task graphs.