Enhancement of hardware modular multiplier radix-4 algorithm for fast RSA cryptosystem

Author

Amer, Kauther M. ; Sharif, Sami M. ; Ashur, Ahmed S.

Author_Institution

Khartoum Univ., Sudan, Libya

fYear

2013

Firstpage

692

Lastpage

696

Abstract

Algorithms and architectures for performing modular multiplication operations are important in residue number system and cryptography. In this paper a new algorithm of Radix-4 MSB modular multiplier using 4-2 compressor is presented. The recoding rules for the radix-4 Booth´s algorithm are used to reduce the number of partial products and improve the total hardware area and time. This new algorithm avoided a carry store and feedback in some algorithms presented in the literature. It is simulated and implemented using MatLab and VHDL.

Keywords

digital arithmetic; multiplying circuits; public key cryptography; 4-2 compressor; MatLab; VHDL; fast RSA cryptosystem; hardware modular multiplier radix-4 algorithm; modular multiplication operations; most significant bit; partial product reduction; radix-4 Booths algorithm; radix-4 MSB modular multiplier; recoding rules; total hardware area improvement; total hardware time improvement; Adders; Algorithm design and analysis; Computer architecture; Cryptography; Field programmable gate arrays; Gold; Hardware; 4–2 Compressor; Booth´s algorithm; FPGA; Modular Multiplication; Multiplier; high-radix multiplier;

fLanguage

English

Publisher

ieee

Conference_Titel

Computing, Electrical and Electronics Engineering (ICCEEE), 2013 International Conference on

Conference_Location

Khartoum

Print_ISBN

978-1-4673-6231-3

Type

conf

DOI

10.1109/ICCEEE.2013.6634024

Filename

6634024