A FPGA ASIC communication channel systems emulator

Author

Page, Kevin J. ; Chau, Paul M.

Author_Institution

California Univ., San Diego, La Jolla, CA, USA

fYear

1993

Firstpage

345

Lastpage

348

Abstract

The authors describe the FPGA implementation of a Communication Channel Systems (CCS) emulator designed for conducting hardware experiments in convolutional forward error correction. This flexible, new test platform provides verification and benchmarking for a wide range of ASIC convolutional decoder designs as well as decoding coprocessors. The system generates test patterns, inserts noise, enables extensive control of signal quantization, and can convolutionally encode with 4 bit soft decisions in any code type from rate 1/2 to 1/6 and any constraint length from 3 through 15

Keywords

application specific integrated circuits; automatic testing; codecs; convolutional codes; coprocessors; decoding; error correction codes; field programmable gate arrays; noise generators; programmable logic arrays; telecommunication channels; telecommunication computing; ATPG; FPGA ASIC; communication channel systems emulator; control of signal quantization; convolutional decoder; convolutional encoding; convolutional forward error correction; decoding coprocessors; hardware experiments; test platform; verification; Application specific integrated circuits; Carbon capture and storage; Communication channels; Convolution; Convolutional codes; Decoding; Field programmable gate arrays; Forward error correction; Hardware; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-1375-5

Type

conf

DOI

10.1109/ASIC.1993.410735

Filename

410735