Low overhead decimal matrix code with dynamic network on chip against multiple cell upsets

This paper presents an efficient decimal matrix code (DMC) technique to obtain the maximum error detection capability. This model can minimize the area overhead of extra circuits using encoder reusing technique (ERT). To maintain the reliability of memories against transient multiple cell upsets decimal matrix code based on divide-symbol is presented. Also the DMC mechanism is suitable for dynamic NOCs where the number and position of processor elements or faulty blocks vary during runtime. Here we present a NOC based on online error detection mechanism and adaptive routing algorithm. NoC is based on routers performing online error detection of routing algorithm and data packet errors. Adaptive routing algorithm allows to bypass faulty components or processor elements dynamically implemented inside the network. The new router architecture is based on additional diagonal state indications and specific logic blocks allowing the reliable operation of the NoC. The main originality in the NoC is that only the permanently faulty parts of the routers are disconnected. Therefore, it maintains a high run time throughput in the NoC without data packet due to self-loopback mechanism inside each router.