Area effective and speed optimized fused Add-Multiply unit

Multipliers are the obligatory component in most of the Digital Signal Processing applications. Designing high speed and low area multipliers are of substantial research interest. For attaining high speed, the Wallace high-speed multiplier utilizing Wallace tree adders are used predominantly. This paper puts forward the design and implementation of high performance Fused Add-Multiply (FAM) unit constituting 4:2 compressor block. The conventional FAM unit using Modified Booth (MB) multiplier incorporating Wallace tree structure with 3:2 compressor suffered by its performance limitations such as high latency and hardware complexity. The speed of traditional Wallace tree structure can be enhanced by employing 4:2 compressor in the FAM design and it attempts to minimize the stage delays of a conventional design using 3:2 compressor. Therefore an area effective and speed optimized FAM unit is proposed to overcome the bottleneck of conventional design. The analysis of both existing and proposed techniques are clearly manifested. FAM units are simulated using Modelsim SE 10.0b and implemented in FPGA using Xilinx ISE for performance analysis.