A 16 bit low-power-consumption digital signal processor for portable terminals

Author

Ishikawa, Toshihiro ; Suzuki, Hidetoshi ; Taki, Hideshi ; Homma, Koichi ; Kabuo, Hideyuki ; Okamoto, Minoru ; Ueda, Katsuhiko ; Asahi, Ryuichi

Author_Institution

Telecom Res. Lab., Matsushita Commun. Ind. Co. Ltd., Yokohama, Japan

fYear

1995

Firstpage

798

Lastpage

802

Abstract

This paper describes a 16-bit fixed point digital signal processor (DSP), which is targeted for telecommunication applications such as modems or low-bit-rate speech CODECs. A variable pipeline multiplier-accumulator (MAC) unit and several additional circuits such as a dual-purpose shift register are used to improve performance per MIPS. The DSP chip is fabricated with 0.5 μm CMOS process and achieves 40 MIPS and 80 MOPS-peak performance at 3.0 V. A PSI-CELP (pitch synchronous innovation code excited linear prediction) speech CODEC can be implemented on this DSP with enough margin

Keywords

CMOS digital integrated circuits; digital signal processing chips; linear predictive coding; mobile radio; pipeline processing; shift registers; speech codecs; telecommunication terminals; 0.5 micron; 16 bit; 3.0 V; 40 MIPS; CMOS process; DSP chip; MIPS; MOPS; PSI-CELP; additional circuits; dual-purpose shift register; low-bit-rate speech codecs; low-power-consumption digital signal processor; modems; peak performance; performance; pitch synchronous innovation code excited linear prediction; portable terminals; telecommunication applications; variable pipeline multiplier-accumulator unit; Decoding; Digital signal processing; Digital signal processing chips; Digital signal processors; Energy consumption; Modems; Pipelines; Shift registers; Speech codecs; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Universal Personal Communications. 1995. Record., 1995 Fourth IEEE International Conference on

Conference_Location

Tokyo

Print_ISBN

0-7803-2955-4

Type

conf

DOI

10.1109/ICUPC.1995.497119

Filename

497119