Title :
A 155.52 Mb/s receiver chip architecture and its simulation methodology for SONET OC-3 application
Author :
Lin, Jizoo ; Lin, Hasn-Fong ; Huang, Chen-Yi ; Peng, Yung-Chow ; Wang, Yuh-Diahn ; Shih, Ming-Tang ; Wang, Chorng-Kuang
Author_Institution :
ITRI, Chutung, Hsinchu, Taiwan
Abstract :
A monolithic receiver chip architecture and its simulation methodology for SONET (Synchronous Optical Network) OC-3 application are described. AGC (Automatic Gain Control) amplifier, timing recovery, and decision circuits will be incorporated in one chip by using a single 5-V power supply double-poly-double-metal 1.0-μm BiCMOS technology. A mixed-mode simulation approach for Workview and Hspice is applied for the whole chip simulations
Keywords :
BiCMOS digital integrated circuits; SONET; application specific integrated circuits; automatic gain control; circuit analysis computing; decision circuits; digital phase locked loops; integrated optoelectronics; optical receivers; timing circuits; 1 micron; 155.52 Mbit/s; 5 V; AGC amplifier; ASIC; BiCMOS technology; Hspice; SONET OC-3 application; Workview; decision circuits; double-poly-double-metal; mixed-mode simulation approach; monolithic receiver chip architecture; simulation methodology; timing recovery; whole chip simulations; Application software; Circuit simulation; Computational modeling; Optical amplifiers; Optical feedback; Optical receivers; Phase locked loops; SONET; Timing; Voltage;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410737
