Circuit considerations for fast, sensitive, low-voltage loads in a distributed power system

Integrated circuits for next generation computer systems subject the power subsystem to extremely large and fast load step transients, with allowable peak voltage deviations of typically less than two percent. These requirements pose a difficult problem for board level designers and are one of the major drivers for distributed power architectures. In this paper, the problem of maintaining tight regulation throughout the transient is examined, and circuit techniques are presented for its solution