A micropower learning vector quantizer for parallel analog-to-digital data compression

Author

Lubkin, Jeremy ; Cauwenberghs, Gert

Author_Institution

Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA

Volume

3

fYear

1998

Firstpage

58

Abstract

An analog VLSI architecture for learning vector quantization (LVQ), with on-chip adaptation and dynamic storage of the analog templates, is presented. The architecture extends to fuzzy ART and Kohonen self-organizing maps through digital programming. The analog memory and adaptive element of the LVQ cell comprise 6 MOS transistors and one capacitor, and provide for robust self-refresh of the dynamic analog storage. Total cell size including distance and adaptive computations is 80×70 lambda in scalable MOSIS technology. Experimental results from a fabricated 16×16 cell prototype in 2 μm CMOS are included

Keywords

ART neural nets; CMOS analogue integrated circuits; VLSI; analogue processing circuits; analogue storage; fuzzy neural nets; learning (artificial intelligence); neural chips; parallel architectures; self-organising feature maps; vector quantisation; 2 micron; CMOS chip; Kohonen self-organizing maps; analog VLSI architecture; analog memory; analog template storage; digital programming; fuzzy ART; learning VQ; learning vector quantization; micropower learning vector quantizer; onchip adaptation; onchip dynamic storage; parallel analog-to-digital data compression; robust self-refresh; scalable MOSIS technology; Analog memory; CMOS technology; Computer architecture; MOS capacitors; MOSFETs; Robustness; Self organizing feature maps; Subspace constraints; Vector quantization; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.703896

Filename

703896