Semi-hierarchical analog simulation method for VHDL-AMS

Hierarchical simulation for analog systems, in general, is impossible. Conservative laws in analog systems generate conservative equations that should be satisfied along with the characteristic equations of the entire model. Conservative equations are not written explicitly by designer; but they are extracted from the physical structure of the model. In order to have a correct set of conservative equations, the entire analog model should be flatted and a single network matrix should be produced. In VHDL-AMS because of special port constrains, it is possible to partition the analog models and utilize a semi-hierarchical analog simulation method. In this paper I explain what this method of partitioning is and how it improves the overall simulation speed.