Fault-tolerant schemes for NoC with a network monitor

Global buses in deep-submicron (DSM) system-on-chip designs consume significant amounts of power, have large propagation delays, and are easy to catch transmission errors due to DSM noise. A comprehensive fault-tolerant mechanism for transient and permanent failures is proposed in this paper. Based on the special NoC with a network monitor, a flit level point-to-point error detection scheme is added to routers to handle transient failures on the data links, while a dynamic routing mechanism is produced to deal with permanent link failures as well. In addition, there is some Build-in testing of the monitor to increase the reliability of the architecture. The result of the experiment demonstrates the advantage of the mechanism in terms of throughput and latency, while the consumptions of area and power overheads are acceptable.