A 531 Mb/s fibre channel SIPO/PISO chip set capable of driving 50 m of shielded twisted pair

Author

Mau Truong ; Yung, Yuk ; Rara, Gary

Author_Institution

National Semiconductor, Santa Clara, CA, USA

fYear

1993

Firstpage

370

Lastpage

373

Abstract

Utilizing National Semiconductor´s 0.8-μm ABiC IV BiCMOS/ECL gate array with an embedded phase-locked loop (PLL), a serial-in-parallel-out (SIPO) and parallel-in-serial-out (PISO) chip set has been developed for 531 Mb/s fibre channel applications. The PISO device includes a high-drive ECL differential output buffer that can be used to drive shielded twisted pair (STP) cable up to 50 m, far exceeding the fibre channel standard wthich specifies 265.625 Mb/s on STP up to 50 m

Keywords

BiCMOS digital integrated circuits; BiCMOS logic circuits; application specific integrated circuits; buffer circuits; data communication; data communication equipment; digital phase locked loops; emitter-coupled logic; logic arrays; optical fibre communication; twisted pair cables; 531 Mbit/s; ASIC; BiCMOS; SIPO/PISO chip set; embedded phase-locked loop; fibre channel; high-drive ECL differential output buffer; parallel-in-serial-out; serial-in-parallel-out; shielded twisted pair; BiCMOS integrated circuits; Cable shielding; Clocks; Logic devices; Optical arrays; Optical buffering; Optical fiber cables; Optical fiber devices; Phase locked loops; Phased arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-1375-5

Type

conf

DOI

10.1109/ASIC.1993.410741

Filename

410741