Hot-carrier-induced gate capacitance variation and its impact on DRAM circuit functionality

In this paper we detail the consequences of hot-carrier effects on gate capacitance variation and it´s impact on the design margin of each constituent circuit of a 64 Mb DRAM. The degradation mechanism, which produces the capacitance imbalance in specific circuit blocks, is the combination of the increase of gate capacitance in PMOSFET, and the decrease of gate capacitance in NMOSFET. The two dimensional device simulation using MEDICI was also carried out to investigate the gate capacitance variation as a function of total trapped charge density and it´s physical length in channel region