Title :
TFSOI CMOS technology for sub-1 V microcontroller circuits
Author :
Huang, W.M. ; Papworth, K. ; Racanelli, M. ; John, J.P. ; Foerstner, J. ; Shin, H.C. ; Park, H. ; Hwang, B.Y. ; Wetteroth, T. ; Hong, S. ; Shin, H. ; Wilson, S. ; Cheng, S.
Author_Institution :
Adv. Custom Technol., Motorola Inc., Mesa, AZ, USA
Abstract :
For the first time, a sub-1 V microcontroller CPU core is demonstrated using Thin-Film-Silicon-On-Insulator (TFSOI) CMOS technology. Yield sensitivity of the microcontroller circuit blocks (including the CPU, SRAM and ROM) to variations of the 0.5 μm process technology is investigated. The low-voltage circuit yield of the CPU is found to be more sensitive to isolation stress-induced device defect leakage than the SRAM and ROM circuits. The stress-induced leakage also causes abnormal frequency vs. VDD behavior with the CPU. CPU yield comparable to bulk CMOS, combined with a ~2× maximum clock frequency enhancement, is achieved with the optimized low-leakage TFSOI process
Keywords :
CMOS digital integrated circuits; SIMOX; circuit optimisation; integrated circuit yield; isolation technology; leakage currents; microcontrollers; 0.5 mum; 0.9 V; CPU core frequency performance; CPU yield; ROM yield; SIMOX substrate; SRAM yield; TFSOI CMOS technology; frequency VDD behavior; isolation stress-induced device defect leakage; low-voltage circuit yield; maximum clock frequency enhancement; microcontroller CPU core; optimized low-leakage TFSOI process; thin-film-silicon-on-insulator CMOS technology; yield sensitivity; CMOS process; CMOS technology; Central Processing Unit; Circuits; Clocks; Frequency; Isolation technology; Microcontrollers; Random access memory; Read only memory;
Conference_Titel :
Electron Devices Meeting, 1995. IEDM '95., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2700-4
DOI :
10.1109/IEDM.1995.497182
