Thermal Stress Analysis of Cu/Low-k Interconnects in 3D-IC Structures

The topics of 3D-IC packages are now widely studied around the world in recent years, not only in electronic packaging areas, but also in bioengineering areas and so on. With the developments of 3D-ICs technologies, packaging effects on 3D-ICs of Cu/low-k interconnects have become a critical reliability issue, especially in the assembly processes and reliability test procedures. In 3D-IC packages, low-k dielectrics are now popularly used to retard the RC delayed effects, increase the bandwidth, reduce the inductance and decrease the power consumption. By using the weaker low-k dielectrics instead of traditional TEOS interlevel dielectrics, packaging induced interfacial delamination in low-k interconnects has been widely observed that raising serious reliability concerns for Cu/low-k chips. In this paper, the thermal induced stresses of Cu/low-k interconnect in 3D-IC structures during reliability test process are obtained by three-dimensional finite element analysis. The packaging induced crack in Cu/low-k structures is also studied. The results show that the interfacial cracks in 3D-ICs significantly impact the distribution of thermal induced stresses in Cu/low-k structures and could have prominent influence on their reliability