DocumentCode
1583700
Title
Performance enhancement of the junctionless surrounding gate transistor with high Ion /Ioff ratio
Author
Surya, A. ; Nirmal, D. ; Charles Pravin, J.
Author_Institution
Dept. of ECE, Karunya Univ., Coimbatore, India
fYear
2015
Firstpage
1
Lastpage
4
Abstract
This paper presents a brief description of a uniformly doped junctionless surrounding gate MOSFET. The proposed device is a thin nanowire has equal doping concentration throughout source, channel and drain region. This device provides very low leakage current, high on current and high on-off current ratio. The absence of the ultra shallow junctions in the conventional MOSFETs makes this device easy to fabricate, by eliminating costly annealing and etching techniques. The simulation result stipulates that junctionless transistor is a promising device for the future electronics.
Keywords
MOSFET; leakage currents; nanowires; semiconductor device models; doping concentration; junctionless transistor; leakage current; on-off current ratio; thin nanowire; ultra shallow junctions; uniformly doped junctionless surrounding gate MOSFET; Etching; Logic gates; Nanoelectronics; Radio frequency; Solids; Transistors; JLSG MOSFET; JLT; Off current; On current; On/Off current ratio; TCAD;
fLanguage
English
Publisher
ieee
Conference_Titel
Innovations in Information, Embedded and Communication Systems (ICIIECS), 2015 International Conference on
Conference_Location
Coimbatore
Print_ISBN
978-1-4799-6817-6
Type
conf
DOI
10.1109/ICIIECS.2015.7193258
Filename
7193258
Link To Document