Silicon-on-insulator by wafer bonding and etch-back

A novel silicon-on-insulator technique utilizing the bonding of oxidized silicon wafers has been investigated. The bonding was achieved by heating in an inert atmosphere a pair of wafers with hydrophilic surfaces, which had been contacted face-to-face. A quantitative method for the evaluation of the surface energy of the bond based on crack propagation theory was developed. The bond strength was found to increase with the bonding temperature from about 60-85 erg/cm² at room temperature to ≈2200 erg/cm² at 1400°C, which is in the same range as the cohesive energy of bulk quartz. The strength was essentially independent of the bond time. Bonds created during a 10 s annealing at 800°C were strong enough to withstand both the thinning of the top wafer to the desired thickness and the subsequent device processing. Three distinct phases of the bonding process were observed. The electrical properties of the bond between the wafers were tested using MOS capacitors. The results were consistent with a negative charge density at the bond interface of approximately 10¹¹ cm^-2. A double etch-back procedure was used to thin the device wafer to the desired thickness. The characteristics of the resulting film are described. CMOS devices made in a 0.3-μm-thick layer had subthreshold slopes of 68 mV/decade (for both n- and p-channel MOS transistors). The effective carrier lifetime was >30 μs in 300-nm-thick Si films, and the interface state density at the Si-film/buried oxide interface was <5×10 ¹⁰ cm^-2