A fully integrated receiver front-end reconfigured by PLL

Author

Han, Seon-Ho ; Kim, Cheon-Soo ; Park, Mun-Yang ; Yu, Hyun-Kyu

Author_Institution

Electron. & Telecommun. Res. Inst., Daejeon, South Korea

fYear

2005

Firstpage

197

Lastpage

200

Abstract

A fully integrated receiver front-end, reconfigured by a frequency locking scheme using a PLL, is implemented in a 0.18 μm triple-well CMOS technology. The receiver front-end is composed of a discretely tunable low noise amplifier (DT-LNA), a quadrature down mixer, and a discretely and continuously tunable frequency synthesizer (DCT-FS) with an integrated DCT-VCO. The front-end measured performances are 2-2.75 GHz tuning range by about 50 MHz steps, 40 dB voltage gain, -25 dBm IIP3, 2.1-2.7 dB DSB NF. The synthesizer features a phase noise of -80 dBc/Hz at in-band and -120 dBc/Hz at 1 MHz offset. The receiver front-end consumes 30 mA from a 1.8 V supply.

Keywords

CMOS integrated circuits; UHF amplifiers; UHF integrated circuits; UHF mixers; circuit tuning; frequency locked loops; frequency synthesizers; phase locked loops; radio receivers; 0.18 micron; 1.8 V; 2 to 2.75 GHz; 2.1 to 2.7 dB; 30 mA; 40 dB; CMOS; DCT-FS; DT-LNA; PLL reconfigured front-end; discretely continuously tunable frequency synthesizer; discretely tunable low noise amplifier; frequency locking; fully integrated receiver front-end; quadrature down mixer; tuning range; CMOS technology; Frequency synthesizers; Gain measurement; Low-noise amplifiers; Noise measurement; Performance evaluation; Phase locked loops; Phase measurement; Tuning; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE

ISSN

1529-2517

Print_ISBN

0-7803-8983-2

Type

conf

DOI

10.1109/RFIC.2005.1489629

Filename

1489629