A comparative performance analysis on 3f multilevel inverter topologies

This paper presents a comparative analysis of the three phase 5 level inverter with reduced number of switches topology and cascaded Multilevel inverter. Here in the reduced number topology, for a large number of output voltage levels, it eventually decrease the number of switches being used. In this case when we compared with cascaded multilevel inverter, the reduced number of switch topology has less number of switches and hence switching loss get reduce, complexity as well as the cost of the system reduced. The Total Harmonic Distortion (THD) of both the circuits show that the reduced no of switches topology gives a better THD. Both the reduced number of switches topology and cascaded topology are compared and simulated, the output is verified using PSIM.