Title :
Design of easily testable VLSI arrays for discrete cosine transform
Author :
Lu, Shyue-Kung ; Wu, Cheng-Wen ; Juo, S.-Y.
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A design-for-testability approach based on the M-testability conditions is applied to the bit-level VLSI systolic arrays for discrete cosine transform (DCT), which guarantee 100% single-cell-fault testability with a minimum number of test patterns. A hardware overhead of no more than 6% is sufficient to make the DCT arrays M-testable. The resulting number of test patterns is only 16, regardless of the size of the DCT array and the internal word length. DCT array testing using the module-fault model also is discussed. M-testable arrays are proposed. An offline fault diagnosis scheme which detects and locates any faulty module in the DCT array by self-comparison is presented
Keywords :
VLSI; design for testability; digital signal processing chips; discrete cosine transforms; fault location; logic testing; systolic arrays; M-testability conditions; design-for-testability approach; discrete cosine transform; hardware overhead; internal word length; module-fault model; offline fault diagnosis scheme; single-cell-fault testability; systolic arrays; test patterns; testable VLSI arrays; Circuit faults; Circuit testing; Computer architecture; Discrete cosine transforms; Fault detection; Fault diagnosis; Hardware; Logic arrays; Systolic arrays; Very large scale integration;
Conference_Titel :
Signals, Systems and Computers, 1992. 1992 Conference Record of The Twenty-Sixth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
0-8186-3160-0
DOI :
10.1109/ACSSC.1992.269072
