Title :
Testability measures reduce test generation time in sequential ATPG
Author :
Macii, Enrico ; Meo, Angelo R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
Abstract :
A technique for estimating the testability of the nodes of a sequential circuit, whose description can be either at the gate-level or at the block-level, is described. Two weight functions are evaluated for each node of the network, and the results obtained are used in an existing set of automatic test pattern generation (ATPG) procedures in order to reduce the test generation time. Experimental results obtained on the ISCAS ´89 standard set of benchmark circuits show the effectiveness of the method
Keywords :
automatic testing; integrated circuit testing; logic testing; sequential circuits; ISCAS ´89 standard set; benchmark circuits; block-level; gate-level; sequential ATPG; test generation time; testability; weight functions; Automatic test pattern generation; Circuit faults; Circuit testing; Controllability; Equations; Sequential analysis; Sequential circuits; Tellurium; Test pattern generators; Time measurement;
Conference_Titel :
Signals, Systems and Computers, 1992. 1992 Conference Record of The Twenty-Sixth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
0-8186-3160-0
DOI :
10.1109/ACSSC.1992.269073
