A fully integrated compact CMOS fractional signal generator for GSM/WCDMA dual-band applications

We present the design, implementation, and measurement of a new compact low power fractional signal generator based on regenerative division and injection locking for GSM/WCDMA dual-band applications. The design generates 2/3 of the input signal frequency, resulting in DC-offset reduction, phase noise improvement, and a reduced tuning range requirement for a VCO in direct conversion architecture. The fractional signal generator is fully integrated with a compact die size of 905×1012 μm² in a 0.18-μm standard CMOS process. It generates local oscillation (LO) frequency from 1.53 GHz to 2.19 GHz with a very low DC power consumption of 10 mW covering the GSM/WCDMA dual-band. The measured noise floor of the generator is -100 dBc/Hz at 10 kHz offset frequency. Design considerations for the operating range and noise floor within the loop bandwidth are discussed in detail.