• DocumentCode
    1583988
  • Title

    Pipeline scheduling techniques in high-level synthesis

  • Author

    Hsu, Yu-Chin ; Jeang, Yuan-Long

  • Author_Institution
    Dept. of Comput. Sci., California, Univ., Riverside, CA, USA
  • fYear
    1993
  • Firstpage
    396
  • Lastpage
    403
  • Abstract
    Pipelining is an effective method to optimize the execution of a loop, especially for digital signal processing (DSP) applications where data enter a circuit regularly. In this tutorial, the authors define the pipeline scheduling problem and the terminologies used in the high-level synthesis. Then they classify current pipeline scheduling algorithms based on the basic techniques used, namely, integer programming based, list scheduling based, probability based, randomized searching based, and transformation based. Future research directions in pipeline scheduling are highlighted
  • Keywords
    application specific integrated circuits; circuit layout CAD; circuit optimisation; high level synthesis; integer programming; integrated circuit layout; pipeline processing; scheduling; ASIC; DSP; algorithms; high-level synthesis; integer programming based; list scheduling based; pipeline scheduling problem; probability based; randomized searching based; transformation based; tutorial; Art; Clocks; Costs; Delay; Hardware; High level synthesis; Pipelines; Radio access networks; Scheduling algorithm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
  • Conference_Location
    Rochester, NY
  • Print_ISBN
    0-7803-1375-5
  • Type

    conf

  • DOI
    10.1109/ASIC.1993.410746
  • Filename
    410746