Experimental results at one GHz on linearizing an nMOS transistor with a parallel pMOS transistor

A simple circuit consisting of an nMOS transistor in parallel with a pMOS transistor is shown to reduce nonlinear distortion. Measured experimental results show more than 10 dB reduction in third order distortion at 1 GHz for a prototype 0.18 micron CMOS integrated circuit. Experimental data further suggest that the relative increase in the third order output intercept point greatly exceeds the corresponding increase in power supply current. Since the proposed circuit is itself a three-terminal device, it can also be used as a building block for larger circuits. Finally, theoretical linearization conditions are presented in terms of the gains and intercept points of the nMOS and pMOS devices.