A cell-based datapath synthesizer for ASICs

A datapath synthesis method that maps an RTL description of an ASIC to a hierarchical netlist is presented. The method partitions the ASIC´s behavior into datapath, mapped to bit-sliced layout or cell-based netlist, and glue logic mapped to cells. This synthesis method performs resource selection and resource sharing, and thus allows the user to explore design space both at the architectural-level and at the gate-level. Also, after placement, the cell-based netlist is further optimized by resizing the gate drives based on timing analysis with post-placement wire capacitances. Examples of datapath synthesis are given, and some experimental results are discussed