Title :
Interconnect optimization in behavioral synthesis of ASICs
Author :
Dalkilic, Mehmet Emin ; Pitchumani, Vijay
Author_Institution :
Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
Abstract :
A new quadratic time global interconnect allocation algorithm for ASIC data path synthesis is presented. The algorithm is based on graph coloring and flipping commutative operation inputs and it has two phases: phase one sets an upper bound on number of multiplexer/bus inputs while phase two minimizes multiplexer/bus inputs as well as the number of two-input multiplexer equivalent of the interconnection network using interconnect merging techniques. The algorithm was applied to problems taken from current literature, and the results compare favorably to those for previous techniques
Keywords :
application specific integrated circuits; constraint handling; graph colouring; high level synthesis; multistage interconnection networks; parallel algorithms; ASIC data path synthesis; behavioral synthesis; constraint satisfaction; flipping commutative operation inputs; global interconnect allocation algorithm; graph coloring; high level synthesis; interconnection network; multiplexer/bus inputs; quadratic time; upper bound; Application specific integrated circuits; Costs; High level synthesis; Merging; Multiplexing; Multiprocessor interconnection networks; Network synthesis; Power system interconnection; Registers; Upper bound;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410752
