Decomposition of logic functions with partial vertex chart

Author

He, Shousheng ; Torkelson, Mats

Author_Institution

Dept. of Appl. Electron., Lund Univ., Sweden

fYear

1993

Firstpage

430

Lastpage

433

Abstract

The partial vertex chart and its application in multi-output logic decomposition is introduced. Necessary condition check for the existence of a simple decomposition is integrated into each step of the chart construction through dispersity measurement, which makes possible the early rejection of the unsatisfied partitions. The subfunctions in disjoint decomposition can be constructed via the compatible sets of partial vertices. A heuristic approach based on the extended chart to search for nondisjoint decomposition is also described

Keywords

field programmable gate arrays; high level synthesis; logic partitioning; minimisation of switching nets; multivalued logic; programmable logic arrays; FPGA; compatible sets; disjoint decomposition; dispersity; early rejection; extended chart; heuristic approach; logic functions; logic synthesis; multi-output logic decomposition; multilevel logic; nondisjoint decomposition; partial vertex chart; subfunctions; unsatisfied partitions; Boolean functions; Computational complexity; Erbium; Field programmable gate arrays; Helium; Independent component analysis; Input variables; Logic functions; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-1375-5

Type

conf

DOI

10.1109/ASIC.1993.410753

Filename

410753