Title :
Three volt to five volt CMOS interface circuit device leakage limited DC power dissipation
Author :
Caravella, James S. ; Quigley, John H.
Author_Institution :
Motorola, Inc., Tempe, AZ, USA
Abstract :
A CMOS interface circuit from three to five volts is presented in which DC power consumption is defined by a single transistor´s OFF leakage current. The interface design provides signal level translation while minimizing propagation delay and power dissipation. Typical propagation delays are on the order of 1.5 ns, with DC power dissipation less than 1 pW. The primary application of the interface is mixed voltage gate arrays with a 3.3-V core and 5.0-V I/Os
Keywords :
CMOS digital integrated circuits; DC-DC power convertors; application specific integrated circuits; buffer circuits; leakage currents; logic arrays; power integrated circuits; 1 pW; 1.5 ns; 3 V; 5 V; ASIC; CMOS interface circuit; OFF leakage current; leakage limited DC power dissipation; mixed voltage gate arrays; propagation delays; signal level translation; single transistor; Batteries; CMOS logic circuits; Energy consumption; Equations; Leakage current; Logic gates; Power dissipation; Propagation delay; Pulse inverters; Voltage;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410756
