A pipelined 45 MHz 24-bit digital signal processing ASIC

Author

Petilli, Stephen G. ; Grimm, Michael J. ; Olson, Erlend M.

Author_Institution

Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA

fYear

1992

Firstpage

666

Abstract

A pipelined DSP gate array that can operate at over 45 MHz and performs 24-b fixed-point arithmetic operations on arrays of complex valued inputs is described. This high performance is achieved by using a 0.8-μm three-level CMOS fabrication process, and by implementing a pipelined FFT butterfly. The partitioning of a Baugh-Wooley two´s complement multiplier is discussed, and testability solutions are developed. It is shown that allowing the ability to bypass segments of the pipe improves testability and adds flexibility over control

Keywords

CMOS integrated circuits; application specific integrated circuits; digital arithmetic; digital signal processing chips; fast Fourier transforms; logic arrays; pipeline processing; 24 bit; 45 MHz; ASIC; CMOS fabrication process; complex valued inputs; fixed-point arithmetic operations; pipelined DSP gate array; pipelined FFT butterfly; testability solutions; two´s complement multiplier; Amplitude shift keying; Application specific integrated circuits; CMOS process; Digital signal processing; Fabrication; Fixed-point arithmetic; Laboratories; Propulsion; Spectral analysis; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 1992. 1992 Conference Record of The Twenty-Sixth Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

0-8186-3160-0

Type

conf

DOI

10.1109/ACSSC.1992.269112

Filename

269112