Title :
Techniques for VLSI design of pipelined IIR digital filters
Author :
Giese, Benjamin S. ; Soderstrand, Michael A.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
Abstract :
Using a design method for pipelining recursive filters, a multiply-add chip was improved from a 40-MHz throughput rate to a 68-MHz rate and a functional compiler design was improved from 24 MHz to 31 MHz. Using this same technique a DSP chip (Sharp LH-9124) implementation of a pipelined FIR filter can be modified to yield pipelined IIR filters which maintain the high throughput rate but offer the better filter responses associated with IIR filters. In the process of applying this new design method to actual VLSI circuits, great insights into pipelining limitations have been obtained
Keywords :
VLSI; digital filters; digital signal processing chips; pipeline processing; 31 MHz; 68 MHz; DSP chip; Sharp LH-9124; VLSI circuits; VLSI design; compiler design; filter responses; multiply-add chip; pipelined FIR filter; pipelined IIR digital filters; pipelining limitations; throughput rate; Circuits; Design methodology; Digital filters; Digital signal processing chips; Finite impulse response filter; IIR filters; Pipeline processing; Throughput; Transfer functions; Very large scale integration;
Conference_Titel :
Signals, Systems and Computers, 1992. 1992 Conference Record of The Twenty-Sixth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
0-8186-3160-0
DOI :
10.1109/ACSSC.1992.269114
