Improved distributed algorithm via Zero-Padding and Multi-Port ROM structure

Inner product operation of vector is a very common method in signal processing, especially in digital filter, and there is a great influence of calculating speed and the occupied resources upon the signal processing system. A traditional serial shift-summation Distributed Algorithm (DA) needs many shift-summation operations but not high in the calculating speed, and complete pipeline parallel structure needs many chip resources of Field Programmable Gates Array (FPGA). For these reasons, an improved method was presented, in which Multi-Port Read Only Memory (MPROM) was synthesized by a Look-Up Table in FPGA to construct a distributed algorithm. What´s more, logic shift operation is replaced by Zero-Padding as to reduce resource occupation and calculation time delay. Through verification by simulation and synthesization, it was shown that the improved algorithm can reach the performance of a complete pipeline parallel structure but only needs a resource occupation of the serial shift-summation structure.