A High Performance SoC On-chip-bus with Multiple Channels and Routing Processes

The reusability of an IP can be increased when it is developed according to a standard bus interface. Up to date, a lot of bus protocol and bus architecture are released though most of them are based on the shared bus architecture and inherit the limitation of performance. We have proposed SNA (SoC network architecture) which is high performance on-chip-bus architecture with SNP (SoC network protocol), to solve the problems of the conventional shared bus. Now, we refine the SNA specification and improve the performance and functionality. The performance of the SNA is improved by supporting multiple routing for bus request of multiple masters. The internal routing logic is also improved so that the gate count is decreased. The proposed SNA employs an extended SNP that supports almost perfect compatibility with AMBA AHB protocol without performance degradation. The hardware complexity of the improved SNA is not increased much by optimizing the current routing logic. The improved SNA works for IPs with the original SNP at its best performance. It guarantees simultaneous multiple channels. Thanks to the small number of interconnection wires, the SNA can also be used for the off-chip bus system