Comparative analysis of three interleaved boost power factor corrected topologies in DCM

Author

Teodorescu, Remus ; Kjær, Søren Bækhoj ; Munk-Nielsen, Stig ; Blaabjerg, Frede ; Pedersen, J.K.

Author_Institution

Dept. of Electr. Energy Conversion, Aalborg Univ., Denmark

Volume

1

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

3

Abstract

The aim of this paper is to analyze in a comparative manner three interleaved boost power factor corrected (PFC) topologies that alleviate some of the conventional boost PFC shortcomings like high input current ripple and current stress. A parallel interleaved topology and two novel serial topologies especially suitable for electronic ballast applications are considered. The boost inductor current and size and the input harmonic current are expressed analytically and compared considering the conventional boost PFC as reference. A practical design example is analyzed using the PSPICE computer simulator

Keywords

DC-DC power convertors; SPICE; inductors; power conversion harmonics; power factor correction; PSPICE computer simulator; boost inductor current; boost inductor size; electronic ballast applications; high input current ripple; high input current stress; input harmonic current; interleaved boost power factor corrected topologies; parallel interleaved topology; serial topologies; Analytical models; Application software; Circuit topology; Computational modeling; Electronic ballasts; Harmonic analysis; Inductors; Reactive power; SPICE; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Electronics Specialists Conference, 2001. PESC. 2001 IEEE 32nd Annual

Conference_Location

Vancouver, BC

ISSN

0275-9306

Print_ISBN

0-7803-7067-8

Type

conf

DOI

10.1109/PESC.2001.953986

Filename

953986