Effects of interface-trapped charge on the SiC MOSFET characteristics

High quality SiC/SiO₂ interfaces are critical to the development of silicon carbide power MOSFETs, IGBTs, and MOS-controlled thyristors. In this work, we examine the effects of thermal stress on the SiC/SiO₂ interface of n-channel MOSFETs that had gate oxides formed by low-pressure chemical-vapor deposition on the silicon face of a 6H-SiC epitaxial layer with subsequent re-oxidation to improve the interface. These devices were found to have a pre-stress mean interface-trap density of 5×10¹¹ cm^-2 eV^-1 at room temperature. The interface-trap density for these oxides was shown to be significantly increased by applying moderate stress (2 MV/cm) at 300°C. The post-stress change in device characteristics is shown to be consistent with the stress-induced increase in interface traps