Architecture of an HDTV Intraframe Predictor for a H.264 Decoder

Multimedia applications need larger and larger bandwidth. The only way to face these demands is to provide more efficient compression algorithms, with the expense of computational complexity. The most efficient compression standard available today is the H.264/AVC. On the architectural point of view, an H.264 decoder can be seen as a system of six main modules: entropy decoder, inverse quantization, inverse transform, motion compensation, intraframe prediction and deblocking filter. These modules can be designed independently and enclosed in IPs, which could be used later to build an H.264 SoC. This paper presents an architecture design of intraframe prediction module. The system was completely built in VHDL language and prototyped over a Xilinx Virtex II Pro FPGA of 27,392 logic elements. The proposed architecture attained the required performance to decode HDTV video stream in realtime, i.e. 1920 times 1080 pixels at 30 frames per second, and used just 20% of the chip